1. Technical Field of the Invention
The present invention relates to static random access memories (SRAM) embodied in MOS technology.
2. Description of Related Art
As is known, a conventional SRAM memory cell comprises six MOS transistors arranged in such a way as to form first and second inverters interconnected between first and second data nodes.
Each inverter comprises a PMOS load transistor connected in series with an NMOS inverter transistor between a DC voltage supply source (DC reference) and a ground reference. The gates of the PMOS and NMOS transistors of each inverter are joined. The common electrodes shared by the NMOS and PMOS transistors constitute a data node.
Two NMOS select transistors provide for the interconnection of the cell with a word line and a bit line, and thus allow reading of the memory point or modification of the latter.
Such cells are advantageous in so far as they are relatively fast. Specifically, the cycle time, that is to say the minimum time between two successive operations of the memory, be it while reading or writing, corresponds to the memory access time, that is to say the time between the moment at which the address is present and the moment at which the item of data read is available at the output of the memory.
However, with this type of memory, the memory is permanent as long as the circuits are powered. Stated otherwise, the data are lost when the memory is no longer powered.
It is therefore necessary to couple these memories to additional nonvolatile memories to which the data are transferred before the power supply is cut off.
In view of the foregoing, there is a need for a nonvolatile SRAM memory cell, that is to say one which is capable of permanently retaining its content.